I am an ASIC designer at NVIDIA, where I help investigate, build and tapeout next-generation GPU hardware. I have contributed to features in Ampere, Hopper and am currently working on next-generation GPUs for machine learning and graphics.

I graduated from Stanford studying something at the intersection of computer architecture, machine learning, systems and VLSI. My current interests are primarily in the following:

• Hardware and system work scheduling
• Sparsity, precision and compression
• HW/Compiler/SW co-design

My background guides my thoughts across the stack in research and design.

In my free time, I travel and hike regularly. During my childhood, I was fortunate to have traveled to many countries, and now I continue to do so inside and outside the US.

Unlike many people’s work, most of my work isn’t public, partly due to how the field of chip architecture has evolved over time (and also because I am terrible at cataloging my work and preparing it for public consumption!). That being said, I hope to share my thoughts, learnings and observations here, and any public facing work so as to get people excited in this field and just raise general awareness!